1. Field of the Invention
The present invention relates to a multi-modulus divider, and more particularly to a multi-modulus divider with an extended and continuous division range.
2. Description of the Prior Art
In order to implement products complying with the increasingly complicated communication specifications, a frequency synthesizer is often demanded to be capable of performing wide-range frequency syntheses of a wide range to match up with all kinds of crystal oscillators, as well as to be capable of synthesizing frequencies of both integral and fractional multiples.
FIG. 1 is a schematic diagram of a programmable dividing circuit 100 commonly used in a frequency synthesizer, wherein the programmable dividing circuit 100 comprises a plurality of divider cells 110 connected in series (six divider cells are included in this example). Each divider cell 110 is controlled by a programming input signal PIN to perform a frequency division with a divisor of 2 or 3. In this example, the least significant bit (LSB) of the programming input signal PIN is PIN—0, and the most significant bit (MSB) of the programming input signal PIN is PIN—5. For example, when the LSB PIN—0 of the programming input signal PIN is 0, the divider cell 110a will divide the input frequency by 2. On the other hand, when the LSB PIN—0 of the programming input signal PIN is 1, the divider 110a will divide the input frequency by 3. In each division cycle, the last divider 110f generates a modulus signal MO6 and transmits the same to the divider 110e. And the modulus signal MO6 is reclocked by the divider 110e to become the modulus signal MO5 and is further transmitted until the divider 100a generates the modulus signal MO1. However, only when the status of the modulus signal is logical “1”, the divider 110 loads programming input signal PIN and performs frequency division according to the instruction of the programming input signal PIN.
The division range of the dividing circuit 100 covers from 2N to (2(N+1)−1). The greatest frequency generated by the dividing circuit 100 is only about two times greater than the least frequency generated by the dividing circuit 100. Therefore, there are many limitations in practical applications.
An improved dividing circuit 200 is shown in FIG. 2. At the modulus signal output terminals of some dividers such as the dividers 110d-100f in this example, are logic circuits comprising OR gates, where the logic circuits are utilized for selectively bypassing the results of frequency division of the dividers 110d-110f. For example, if the PIN—6 is set to “0”, no matter what status of the modulus signal MO6 is, the logic gate 222f outputs “1” to the modulus signal input terminal of the divider 110e. This behavior means that the divider cell 110f is abandoned and the divider cell 110a-110e will generate the dividing output of the dividing circuit 200. When the values of the PIN—6 and PIN—5 are both set to “0”, no matter what values of the modulus signals MO5 and the MO6 are, the logic gate 222e outputs “1” to the modulus signal input terminal of the divider cell 110d, which means that the divider cell 110e and the divider cell 110f are both abandoned. Therefore, the number of the divider cells in the dividing circuit 200 that truly influence the output frequency can be properly adjusted by setting the programming input signal PIN. Accordingly, compared to the diving circuit shown in FIG. 1, the division range of the dividing circuit 200 can be extended down to 2M, wherein M represents the number of divider cells that cannot be bypassed. It should be noted that N>M≧1.
Although the dividing circuit 200 has an advantage of a wide range by means of bypassing some divider cells, it is strictly limited when the architecture of the dividing circuit 200 is applied to a fraction-N frequency synthesizer. This is because the fractional-N frequency synthesizer requires the operation result of each division cycle to be correct. However, since the divisor changes in each cycle, the same divisor cannot wait more cycles for the operation result to become correct—such occurrence is one of the biggest differences between the fractional-N frequency synthesizer and the general frequency synthesizer. The modulus signals of the bypassed divider cells in the dividing circuit 200 do not certainly have logical “1” in each division cycle, so some divisors may not be loaded correctly. This error occurs while the division ratio hops from less than 2K to greater than or equal to 2K, wherein K is a positive integer. An example of K=6 is shown in FIG. 3, which illustrates the waveforms of modulus signals MO1, MO2, . . . , and MO6 of the dividing circuit 200 when the value of the divisor hops from 63 to 64. As the divider cell 110f is bypassed in the cycles when the divisor is less than 64 (e.g., the division cycles of 62 or 63 in the figure), the modulus signal MO6 depends only on FO6, such that the cycle of the modulus signal MO6 is twice or triple of the desired division cycle. At this moment, the cycles of MO1, MO2, . . . , and MO5 are desired cycles corresponding to the input PIN. As a result, when entering the cycle of the divisor of 64, the modulus signal MO6 stays at logical “0”; therefore the divider cell 110 cannot further load the value of the PIN—5 correctly. In order not to have a divisor of zero, the dividing circuit 200 will force the PIN—4 to be 1. The division cycle originally corresponding to a divisor of 64 becomes the division cycle corresponding to a divisor of 32, making the multi-modulus divider output a wrong frequency. For the entire frequency synthesizer, this kind of error usually reflects on the output via the mechanism of narrow-band frequency modulation (FM), causing the overall phase noise to become much worse and unendurable, and even causing out-of-lock.
In short, although the division range of the dividing circuit 200 appears to cover from 2M to 2(N+1)−1, it is in fact ensured that no error occurs on the output frequency of the multi-modulus divider only when the divisor variance does not exceed respective intervals of [2M, (2(M+1)−1)], [2M+1, (2(M+2)−1)], . . . , and [2N, (2(N+1)−1)]. A correct division, however, cannot be guaranteed in one division cycle for each division in the entire division range of 2M to 2(N+1)−1.
The current trend in modern applications is that a single circuit must be able to support different reference frequencies (i.e., the reference frequency changes in accordance with different standards of crystal oscillators, such as 13 MHz or 26 MHz for GSM, 19.2 to 19.8 MHz for CDMA, 16 MHz for GPS, and 15.36 MHz for WCDMA). Taking a GPS chip for example, it uses only one crystal oscillator of 16 MHz in the single application of GPS, while having to support the reference frequency of a mobile phone, such as 13 MHz or 26 MHz, when the chip is collocated in a mobile phone. If the fractional-N synthesizer supports more standards of crystals, it inevitably faces changes in the division value (i.e., divisor), which may hop from less than 2K to greater than or equal to 2K; as a result, the above-mentioned dividing circuit 200 is not suitable anymore.